1. Field of Invention
The present invention relates to an illegal address detector for semiconductor memories, and more particularly to an illegal address detector for semiconductor memories having word depths that are not a power of two.
2. State of the Art
Semiconductor memories have conventionally been designed to include a number of memory words that is a power of two, since an address input having n address lines maybe used to uniquely address 2.sup.n memory words. In custom integrated circuit design where user requirements are well-known, it is not uncommon for a particular application to require a number of memory words greater than a power of two but considerably less than a next power of two. In such an instance, space savings may be realized by designing the memory to have only the number of memory words required such that space that would have otherwise been used for additional memory words to reach the next power of two may be devoted to other purposes. Custom design of semiconductor memories may be readily performed using computer-aided design tools known as memory compilers.
When a semiconductor memory is designed to have a number of memory words that is not a power of two, provision must be made for the user's inadvertently addressing memory locations that do not exist in the memory. Otherwise, the output of the memory will be unpredictable, and in the extreme case, damage to the semiconductor memory may even result. In memories using precharged bit lines, for example, if a word that does not exist in the memory is addressed, the bits lines both remain high, and may float from their precharged high state to unpredictable values. Even if the semiconductor memory remains unharmed, higher power consumption nevertheless results.
One possible solution to this problem would be to add a circuit that would sense the floating bit lines and pull one of them low. Such a circuit incurs a speed penalty, however, in that it slows down the normal operation of the memory. Time must be allowed for one of the bit lines to go low before the circuit can begin to sense that this has not happened and that one of the bit lines must be pulled low. If the memory is being operated at top speed, such a circuit, although it may solve the problem of higher power consumption, is unable to solve the problem of unpredictable outputs from the memory.
What is needed then, is a simple, easily compiled circuit that may be included in semiconductor memories having a word depth not equal to a power of two to make the memory outputs predictable, and to make the memory operate within the same specifications (power, speed, etc.) no matter what address is applied.